Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers

Introduction

Phase noise and jitter are two key parameters that affect the performance of PLL-based frequency synthesizers. Phase noise is a measure of the unwanted frequency modulation of the output signal, while jitter is a measure of the variation in the output signal's phase. Both phase noise and jitter can degrade the performance of communication systems, so it is important to be able to predict their values.

Predicting Phase Noise

Phase noise is caused by a number of factors, including:

• Thermal noise in the oscillator
• Flicker noise in the oscillator
• Noise in the PLL loop filter
• Noise in the reference signal

The total phase noise of a PLL-based frequency synthesizer can be calculated using the following formula:

L(f) = L(f)_osc + L(f)_loop + L(f)_ref

where:

• L(f) is the total phase noise of the synthesizer
• L(f)_osc is the phase noise of the oscillator
• L(f)_loop is the phase noise of the PLL loop filter
• L(f)_ref is the phase noise of the reference signal

The phase noise of the oscillator is typically the dominant source of phase noise in a PLL-based frequency synthesizer. The phase noise of the oscillator can be measured using a spectrum analyzer.

Predicting Jitter

Jitter is caused by a number of factors, including:

• Phase noise
• Clock jitter
• Reference signal jitter

The total jitter of a PLL-based frequency synthesizer can be calculated using the following formula:

J = J_phase + J_clock + J_ref

where:

• J is the total jitter of the synthesizer
• J_phase is the jitter caused by phase noise
• J_clock is the jitter caused by clock jitter
• J_ref is the jitter caused by reference signal jitter

The jitter caused by phase noise is typically the dominant source of jitter in a PLL-based frequency synthesizer. The jitter caused by phase noise can be reduced by using a low-noise oscillator and by using a PLL loop filter with a high bandwidth.

Common Mistakes to Avoid

When predicting the phase noise and jitter of a PLL-based frequency synthesizer, it is important to avoid the following common mistakes:

• Ignoring the phase noise of the reference signal. The phase noise of the reference signal can be a significant source of phase noise in the synthesizer.
• Using a PLL loop filter with too high a bandwidth. A PLL loop filter with too high a bandwidth will reduce the jitter, but it will also increase the phase noise.
• Using an oscillator with too low a frequency. A low-frequency oscillator will have a higher phase noise than a high-frequency oscillator.

How to Step-by-Step Approach

To predict the phase noise and jitter of a PLL-based frequency synthesizer, follow these steps:

1. Measure the phase noise of the oscillator. The phase noise of the oscillator can be measured using a spectrum analyzer.
2. Calculate the phase noise of the PLL loop filter. The phase noise of the PLL loop filter can be calculated using the following formula:

L(f)_loop = K_vco / (2 * π * f_loop * C * R)

where:

• K_vco is the VCO gain
• f_loop is the PLL loop bandwidth
• C is the loop filter capacitor
• R is the loop filter resistor

3. Calculate the phase noise of the reference signal. The phase noise of the reference signal can be obtained from the manufacturer's datasheet.
4. Calculate the total phase noise of the synthesizer. The total phase noise of the synthesizer can be calculated using the following formula:

L(f) = L(f)_osc + L(f)_loop + L(f)_ref

5. Calculate the jitter caused by phase noise. The jitter caused by phase noise can be calculated using the following formula:

J_phase = sqrt(2 * π * f_m * L(f_m))

where:

• f_m is the modulation frequency
• L(f_m) is the phase noise at the modulation frequency

6. Calculate the jitter caused by clock jitter. The jitter caused by clock jitter can be calculated using the following formula:

J_clock = J_rms / (2 * π * f_clk)

where:

• J_rms is the RMS jitter of the clock
• f_clk is the clock frequency

7. Calculate the jitter caused by reference signal jitter. The jitter caused by reference signal jitter can be calculated using the following formula:

J_ref = J_rms / (2 * π * f_ref)

where:

• J_rms is the RMS jitter of the reference signal
• f_ref is the reference signal frequency

8. Calculate the total jitter of the synthesizer. The total jitter of the synthesizer can be calculated using the following formula:

J = J_phase + J_clock + J_ref

FAQs

1. What is the difference between phase noise and jitter?

Phase noise is a measure of the unwanted frequency modulation of the output signal, while jitter is a measure of the variation in the output signal's phase.

2. What are the main sources of phase noise in a PLL-based frequency synthesizer?

The main sources of phase noise in a PLL-based frequency synthesizer are the oscillator, the PLL loop filter, and the reference signal.

3. What are the main sources of jitter in a PLL-based frequency synthesizer?

The main sources of jitter in a PLL-based frequency synthesizer are phase noise, clock jitter, and reference signal jitter.

4. How can I reduce the phase noise of a PLL-based frequency synthesizer?

You can reduce the phase noise of a PLL-based frequency synthesizer by using a low-noise oscillator, by using a PLL loop filter with a high bandwidth, and by using a reference signal with low phase noise.

5. How can I reduce the jitter of a PLL-based frequency synthesizer?

You can reduce the jitter of a PLL-based frequency synthesizer by using a low-noise oscillator, by using a PLL loop filter with a high bandwidth, and by using a clock and reference signal with low jitter.

Stories and What We Learn

Story 1

A customer came to us with a problem. They were using a PLL-based frequency synthesizer in a communication system, but they were experiencing excessive phase noise and jitter. We helped them to troubleshoot the problem and found that the problem was caused by a faulty oscillator. We replaced the oscillator with a new one, and the phase noise and jitter were reduced to acceptable levels.

What we learn: It is important to use a high-quality oscillator in a PLL-based frequency synthesizer. A faulty oscillator can cause excessive phase noise and jitter.

Story 2

A customer came to us with a problem. They were using a PLL-based frequency synthesizer in a radar system, but they were experiencing excessive jitter. We helped them to troubleshoot the problem and found that the problem was caused by a clock with too much jitter. We replaced the clock with a new one, and the jitter was reduced to acceptable levels.

What we learn: It is important to use a low-jitter clock in a PLL-based frequency synthesizer. A clock with too much jitter can cause excessive jitter.

Story 3

A customer came to us with a problem. They were using a PLL-based frequency synthesizer in a navigation system, but they were experiencing excessive phase noise and jitter. We helped them to troubleshoot the problem and found that the problem was caused by a noisy reference signal. We replaced the reference signal with a new one, and the phase noise and jitter were reduced to acceptable levels.

What we learn: It is important to use a low-noise reference signal in a PLL-based frequency synthesizer. A noisy reference signal can cause excessive phase noise and jitter.

Conclusion

Predicting the phase noise and jitter of PLL-based frequency synthesizers is an important part of designing and using these devices. By understanding the factors that affect phase noise and jitter, you can design and use PLL-based frequency synthesizers to achieve the best possible performance.

Tables

Table 1: Typical Phase Noise of Different Types of Oscillators

Table 2: Typical Jitter of Different Types of Clocks

Table 3: Typical Phase Noise and Jitter of PLL-Based Frequency Synthesizers